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4 MEG x 4 FPM DRAM
DRAM
FEATURES
* Industry-standard x4 pinout, timing, functions, and packages * High-performance, low-power CMOS silicon-gate process * Single power supply (+3.3V 0.3V or +5V 0.5V) * All inputs, outputs and clocks are TTL-compatible * Refresh modes: RAS#-ONLY, HIDDEN and CAS#BEFORE-RAS# (CBR) * Optional self refresh (S) for low-power data retention * 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh) * FAST-PAGE-MODE (FPM) access * 5V tolerant inputs and I/Os on 3.3V devices
MT4LC4M4B1, MT4C4M4B1 MT4LC4M4A1, MT4C4M4A1
For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.html
PIN ASSIGNMENT (Top View) 24/26-Pin SOJ
VCC DQ0 DQ1 WE# RAS# **NC/A11 A10 A0 A1 A2 A3 VCC
24/26-Pin TSOP
VCC VSS DQ0 DQ3 DQ1 DQ2 WE# CAS# RAS# OE# **NC/A11 A9 A10 A0 A8 A1 A7 A2 A6 A3 A5 VCC A4 VSS 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 VSS DQ3 DQ2 CAS# OE# A9 A8 A7 A6 A5 A4 VSS
1 2 3 4 5 6 8 9 10 11 12 13
26 25 24 23 22 21 19 18 17 16 15 14
OPTIONS
* Voltage 3.3V 5V * Refresh Addressing 2,048 (2K) rows 4,096 (4K) rows * Packages Plastic SOJ (300 mil) Plastic TSOP (300 mil) * Timing 50ns access 60ns access * Refresh Rates Standard Refresh Self Refresh (128ms period)
MARKING
LC C B1 A1 DJ TG -5 -6 None S*
**NC on 2K refresh and A11 on 4K refresh options.
4 MEG x 4 FPM DRAM PART NUMBERS
PART NUMBER MT4LC4M4B1DJ-6 MT4LC4M4B1DJ-6 S MT4LC4M4B1TG-6 MT4LC4M4B1TG-6 S MT4LC4M4A1DJ-6 MT4LC4M4A1DJ-6 S MT4LC4M4A1TG-6 MT4C4M4A1TG-6 S MT4C4M4B1DJ-6 MT4C4M4B1DJ-6 S MT4C4M4B1TG-6 MT4C4M4B1TG-6 S MT4C4M4A1DJ-6 MT4C4M4A1DJ-6 S MT4C4M4A1TG-6 MT4C4M4A1TG-6 S REFRESH VCC ADDRESSING PACKAGE REFRESH 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 5V 5V 5V 5V 5V 5V 5V 5V 2K 2K 2K 2K 4K 4K 4K 4K 2K 2K 2K 2K 4K 4K 4K 4K SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP Standard Self Standard Self Standard Self Standard Self Standard Self Standard Self Standard Self Standard Self
NOTE: 1. The 4 Meg x 4 FPM DRAM base number differentiates the offerings in one place--MT4LC4M4B1. The fifth field distinguishes various options: B1 designates a 2K refresh and A1 designates a 4K refresh for FPM DRAMs. 2. The # symbol indicates signal is active LOW. *Contact factory for availability
Part Number Example:
MT4LC4M4B1DJ
KEY TIMING PARAMETERS
SPEED -5 -6
tRC 84ns 110ns tRAC
50ns 60ns
tPC 20ns 35ns
tAA 25ns 30ns
tCAC
13ns 15ns
tRP 30ns 40ns
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
GENERAL DESCRIPTION
The 4 Meg x 4 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the column address (the latter 11 bits for 2K and the latter 10 bits for 4K; address pins A10 and A11 are "Don't Care"). READ and WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. If WE# goes LOW prior to CAS# going LOW, the output pins remain open (High- Z) until the next CAS# cycle, regardless of OE#. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# is taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z regardless of the state of OE#. During LATE WRITE or READ-MODIFY-WRITE cycles, OE# must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READMODIFY-WRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data outputs will drive read data from the accessed location. The four data inputs and the four data outputs are routed through four pins using common I/O, and pin direction is controlled by WE# and OE#. The MT4LC4M4B1 and MT4LC4M4A1 must be refreshed periodically in order to retain stored data. Additional columns may be accessed by providing valid column addresses, strobing CAS# and holding RAS# LOW, thus executing faster memory cycles. Returning RAS# HIGH terminates the page mode of operation, i.e., closes the page.
DRAM REFRESH
Preserve correct memory cell data by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#-ONLY, CBR, or HIDDEN) so that all combinations of RAS# addresses (2,048 for 2K and 4,096 for 4K) are executed within tREF (MAX), regardless of sequence. The CBR and SELF REFRESH cycles will invoke the internal refresh counter for automatic RAS# addressing. An optional self refresh mode is also available the "S" version. The self refresh feature is initiated by performing a CBR REFRESH cycle and holding RAS# LOW for the specified tRASS. The "S" option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 128ms, or 31.25s per row for a 4K refresh and 62.5s per row for a 2K refresh, when using a distributed CBR REFRESH. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. The self refresh mode is terminated by driving RAS# HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS# LOW-to-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exiting self refresh. However, if the DRAM controller utilizes RAS#-ONLY or burst CBR refresh sequence, all rows must be refreshed with a refresh rate of tRC minimum prior to resuming normal operation.
FAST PAGE MODE ACCESS
Page operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a rowaddress-defined page boundary. The page cycle is always initiated with a row address strobed in by RAS#, followed by a column address strobed in by CAS#.
STANDBY
Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the RAS# HIGH time.
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
FUNCTIONAL BLOCK DIAGRAM - 2K REFRESH
WE# CAS#
DATA-IN BUFFER
4
NO. 2 CLOCK GENERATOR
DATA-OUT BUFFER
4 4
DQ0 DQ1 DQ2 DQ3
OE# COLUMNADDRESS BUFFER(11) REFRESH CONTROLLER
COMPLEMENT SELECT
11 11 ROWADDRESS BUFFERS (11)
ROW SELECT (2 of 4,096)
ROW DECODER
2,048 2,048 2,048 2,048
11
2,048
4,096 x 1,024 x 4 MEMORY ARRAY
RAS#
NO. 1 CLOCK GENERATOR
ROW TRANSFER (1 OF 2) ROW TRANSFER (2 OF 2)
VDD VSS
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
11
10 1
COLUMN DECODER
1,024
4
SENSE AMPLIFIERS I/O GATING
1,024 REFRESH COUNTER
FUNCTIONAL BLOCK DIAGRAM - 4K REFRESH
WE# CAS#
DATA-IN BUFFER
4
NO. 2 CLOCK GENERATOR
DATA-OUT BUFFER
4 4
DQ0 DQ1 DQ2 DQ3
OE# COLUMNADDRESS BUFFER(10) REFRESH CONTROLLER
COMPLEMENT SELECT
12
ROW SELECT (1 of 4096)
ROW DECODER
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
10
10
COLUMN DECODER
1,024
4
SENSE AMPLIFIERS I/O GATING
1,024 REFRESH COUNTER 4,096 x 1,024 x 4 MEMORY ARRAY
12
ROWADDRESS BUFFERS (12)
4,096 4,096
12
4,096
RAS#
NO. 1 CLOCK GENERATOR
VDD Vss
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Pin Relative to VSS 3.3V............................................. ......... -1V to +4.6V 5V................................................ ............ -1V TO +7V Voltage on NC, Inputs or I/O Pins Relative to VSS 3.3V............................................. ......... -1V to +5.5V 5V................................................ ............ -1V TO +7V Operating Temperature, TA (ambient) .... 0C to +70C Storage Temperature (plastic) ............ -55C to +150C Power Dissipation ................................................... 1W *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 5, 6) (VCC (MIN) VCC VCC (MAX)) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Valid Logic 1; All inputs, I/Os and any NC INPUT LOW VOLTAGE: Valid Logic 0; All inputs, I/Os and any NC INPUT LEAKAGE CURRENT: Any input at VIN [0V VIN VCC (MAX)]; All other pins not under test = 0V OUTPUT HIGH VOLTAGE: IOUT = -2mA OUTPUT LOW VOLTAGE: IOUT = 2mA OUTPUT LEAKAGE CURRENT: Any output at VOUT [0V VOUT VCC (MAX)]; DQ is disabled and in High-Z state SYMBOL VCC VIH VIL II 3.3V MIN MAX 3 2 -1.0 -2 3.6 5.5 0.8 2 MIN 4.5 2.4 -0.5 -2 5V MAX UNITS NOTES 5.5 Vcc+1 0.8 2 V V V A 24 24
VOH VOL IOZ
2.4 - -5
- 0.4 5
2.4 - -5
- 0.4 5
V V A
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3, 5, 6) [Vcc (MIN) Vcc Vcc (MAX)] 3.3V PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS# = VIH) STANDBY CURRENT: CMOS (non-"S" version only) (RAS# = CAS# = other inputs = VCC - 0.2V) STANDBY CURRENT: CMOS ("S" version only) (RAS# = CAS# = other inputs = VCC - 0.2V) OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) OPERATING CURRENT: FAST PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) REFRESH CURRENT: Extended ("S" version only) Average power supply current: CAS# = 0.2V or CBR cycling; RAS# = tRAS (MIN); WE# = VCC - 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open) REFRESH CURRENT: Self ("S" version only) Average power supply current: CBR with RAS# tRASS (MIN) and CAS# held LOW; WE# = VCC - 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open) 5V
2K 4K 2K 4K SYM SPEED REFRESH REFRESH REFRESH REFRESH UNITS NOTES ICC1 ICC2 ICC2 ALL ALL ALL -5 -6 -5 -6 -5 -6 -5 -6 ALL ICC7
tRC
1 500 150 110 100 110 100 110 100 110 100 300
1 500 150 90 80 100 90 90 80 90 80 300
1 500 150 140 130 110 100 140 130 140 130 300
1 500 150 120 110 100 90 120 110 120 110 300
mA mA A
ICC3
mA
23
ICC4
mA
23
ICC5
mA
ICC6
mA A
4, 7 4, 7
62.5
31.25
62.5
31.25
s
23
ICC8
ALL
300
300
300
300
A
4, 7
CAPACITANCE
(Note: 6) PARAMETER Input Capacitance: Address pins Input Capacitance: RAS#, CAS#, WE#, OE# Input/Output Capacitance: DQ SYMBOL CI1 CI2 CIO MAX 5 7 7 UNITS pF pF pF
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12) [Vcc (MIN) Vcc Vcc (MAX)]
AC CHARACTERISTICS PARAMETER Access time from column address Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# LOW to "Don't Care" during Self Refresh CAS# hold time (CBR Refresh) CAS# to output in Low-Z CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable OE# hold time from WE# during READ-MODIFY-WRITE cycle Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle FAST-PAGE-MODE READ or WRITE cycle time FAST-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (FAST PAGE MODE) RAS# pulse width during Self Refresh Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period (2,048 cycles) Refresh period (4,096 cycles) -5 SYMBOL tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCHD tCHR tCLZ tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH
tOFF tORD tPC tPRWC tRAC tRAD tRAH tRAS tRASP tRASS tRC tRCD tRCH tRCS tREF tREF
-6 MAX 25 MIN 45 0 0 49 13 15 10 10 15 10 0 10 5 45 5 35 10 10 0 0 10 12 0 0 25 56 12 10 60 60 100 104 14 0 0 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ms ms NOTES
MIN 38 0 0 42 8 8 15 8 0 8 5 38 5 28 8 8 0 0 8 0 0 20 47 9 9 50 50 100 84 11 0 0
18
10,000
4 22 13
28
35
4 18 19 19 22 20
12 12
15 15
17, 22
50
60
15
10,000 125,000
10,000 125,000
14 16
32 64
32 64
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12) [Vcc (MIN) Vcc Vcc (MAX)]
AC CHARACTERISTICS PARAMETER Refresh period "S" version RAS# precharge time RAS# to CAS# precharge time RAS# precharge time exiting Self Refresh READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WRITE command pulse width WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) -5 SYMBOL tREF tRP tRPC tRPS tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWP tWRH tWRP MIN 30 5 90 0 13 116 67 13 2 8 38 0 5 8 8 MAX 128 MIN 40 5 105 0 15 140 79 15 2 10 45 0 5 10 10 -6 MAX 128 UNITS ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 140
16
19
50
50
18 4, 23 4, 23
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
NOTES
1. 2. 3. All voltages referenced to VSS. This parameter is sampled. VCC = +3.3V or 5.0V; f = 1 MHz. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. Enables on-chip refresh and address counters. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. An initial pause of 100s is required after powerup, followed by eight RAS# refresh cycles (RAS#ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. AC characteristics assume tT = 5ns. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. If CAS# = VIH, data output is High-Z. If CAS# = VIL, data output may contain data from the last valid READ cycle. Measured with a load equivalent to two TTL gates, 100pF and VOL = 0.8V and VOH = 2V. If CAS# is LOW at the falling edge of RAS#, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS# must be pulsed HIGH for tCP. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD limit, tAA and tCAC must always be met. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC, and tCAC must always be met. Either tRCH or tRRH must be satisfied for a READ cycle. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. tWCS, tRWD, tAWD, and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. tRWD, tAWD, and tCWD apply to READ-MODIFY-WRITE cycles. If tWCS tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tRWD tRWD (MIN), tAWD tAWD (MIN), and tCWD tCWD (MIN), the cycle is a READ-MODIFYWRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of data-out is indeterminate. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD, and tAWD are not applicable in a LATE WRITE cycle. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. If OE# is tied permanently LOW, LATE WRITE, or READ-MODIFY-WRITE operations are not permissible and should not be attempted. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. The 3ns minimum is a parameter guaranteed by design. Column address changed once each cycle. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 10ns, and the pu lse width cannot be greater than one third of the cycle rate.
16. 17.
4. 5.
6.
18.
7. 8.
9.
10. 11. 12. 13.
19.
20.
14.
21.
22. 23. 24.
15.
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
READ CYCLE
tRC tRAS V IH V IL tCSH tRSH tCRP V IH V IL tAR tASR V IH V IL tRAD tRAH tASC tCAH tRCD tCAS tRRH tRP
RAS#
CAS#
ADDR
ROW tRCS
COLUMN tRCH
ROW
WE#
V IH V IL tAA tRAC tCAC tCLZ tOFF
V DQ V IOH IOL
OPEN
VALID DATA
OPEN
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL
tAA tAR tASC tASR tCAC tCAH tCAS tCLZ tCRP tCSH tOD tOE
-6 MAX 25 MIN 45 0 0 13 15 10 10 0 5 45 12 12 0 15 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tOFF tRAC tRAD tRAH tRAS tRC tRCD tRCH tRCS tRP tRRH tRSH
-5 MIN 0 9 9 50 84 11 0 0 30 0 13 10,000 MAX 12 50 MIN 0 12 10 60 104 14 0 0 40 0 15
-6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 8 8 0 5 38 0
10,000
10,000
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
EARLY WRITE CYCLE
tRC tRAS V IH V IL tCSH tRSH tCRP V IH V IL tAR tASR ADDR V IH V IL tRAD tRAH tASC tCAH tRCD tCAS tRP
RAS#
CAS#
ROW
COLUMN tCWL tRWL tWCS tWCR tWCH tWP
ROW
WE#
V IH V IL tDS tDH
V DQ V IOH IOL
VALID DATA
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL
tAR tASC tASR tCAH tCAS tCRP tCSH tCWL tDH tDS tRAD
-6 MAX MIN 45 0 0 10,000 10 10 5 45 10 10 0 12 10,000 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tRAH tRAS tRC tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP
-5 MIN 9 50 84 11 30 13 13 8 38 0 5 MAX 10,000 MIN 10 60 104 14 40 15 15 10 45 0 5
-6 MAX 10,000 UNITS ns ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 8 8 5 38 8 8 0 9
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC tRAS V IH V IL tCSH tRSH tCAS tRP
RAS#
tCRP V IH V IL tAR tRAD tRAH
tRCD
CAS#
tASR ADDR V IH V IL
tASC
tCAH
ROW
COLUMN tRWD tCWD tAWD tCWL tRWL tWP
ROW
tRCS
WE#
V IH V IL tAA tRAC tCAC tCLZ tDS VALID D OUT tOE V IH V IL tOD tDH
V DQ V IOH IOL
OPEN
VALID D IN tOEH
OPEN
OE#
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA tAR tASC
tASR tAWD tCAC tCAH tCAS tCLZ tCRP tCSH tCWD tCWL tDH tDS
-6 MAX 25 MIN 45 0 0 49 13 15 10 10 0 5 45 35 10 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tOD tOE tOEH tRAC tRAD tRAH tRAS tRCD tRCS tRP tRSH tRWC tRWD tRWL tWP
-5 MIN 0 8 50 9 9 50 11 0 30 13 116 67 13 5 10,000 12 10 60 14 0 40 15 140 79 15 5 MAX 12 12 MIN 0 10
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 42 8 8 0 5 38 28 8 8 0
10,000
10,000
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
FAST-PAGE-MODE READ CYCLE
tRASP V IH V IL tCSH tCRP V IH V IL tAR tASR ADDR V IH V IL tRAD tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP
RAS#
CAS#
ROW
COLUMN
COLUMN tRCS tRCH
COLUMN tRCS
ROW tRRH
tRCS WE# V IH V IL
tRCH
tRCH
tAA tRAC tCAC tCLZ DQ V IOH V IOL OPEN tOE V IH V IL VALID DATA tOD tOFF tCLZ
tAA tCPA tCAC tOFF tCLZ VALID DATA tOD
tAA tCPA tCAC tOFF
tOE
tOE
VALID DATA tOD
OPEN
OE#
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA tAR tASC
tASR tCAC tCAH tCAS tCLZ tCP tCPA tCRP tCSH tOD
-6 MAX 25 MIN 45 0 0 13 15 10 10 0 10 28 35 5 45 12 0 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOE tOFF tPC
tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRRH tRSH
-5 MIN 0 20 9 9 50 11 0 0 30 0 13 125,000 MAX 12 12 50 12 10 60 14 0 0 40 0 15 MIN 0 25
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 8 8 0 8 5 38 0
10,000
125,000
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
FAST-PAGE-MODE EARLY WRITE CYCLE
tRASP V IH V IL tCSH tCRP V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP
RAS#
CAS#
ROW
COLUMN tCWL tWCH tWP
COLUMN tCWL tWCH tWP
COLUMN tCWL tWCH tWP
ROW
tWCS
tWCS
tWCS
WE#
V IH V IL tDS tWCR tDH tDS tDH tDS tRWL tDH
V DQ V IOH IOL V IH V IL
VALID DATA
VALID DATA
VALID DATA
OE#
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAR tASC tASR
tCAH tCAS tCP tCRP tCSH tCWL tDH tDS tPC
-6 MAX MIN 45 0 0 10 10 10 5 45 10 10 0 25 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tRAD tRAH tRASP
tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP
-5 MIN 9 9 50 11 30 13 13 8 38 0 5 MAX MIN 12 10 60 14 40 15 15 10 45 0 5
-6 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 8 8 8 5 38 8 8 0 20
125,000
125,000
10,000
10,000
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
13
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP V IH V IL tCSH tCRP V IH V IL tAR tRAD tRAH tRCD tCAS NOTE 1 tCP tPC tPRWC tCAS tRSH tCP tCAS tCP tRP
RAS#
CAS#
tASR ADDR V IH V IL
tASC
tCAH
tASC
tCAH
tASC
tCAH
ROW
COLUMN tRWD tRCS tCWL tWP tAWD tCWD
COLUMN
COLUMN tRWL tCWL tAWD tCWD tWP
ROW
tCWL tWP tAWD tCWD
WE#
V IH V IL tAA tRAC tDH tDS tCAC tCLZ tAA tCPA tCAC tCLZ
VALID D OUT VALID DIN VALID D OUT VALID D IN
tAA tDH tDS tCPA tCAC tCLZ
VALID D OUT VALID D IN
tDH tDS
DQ
V IOH V IOL
OPEN
OPEN
tOD tOE OE# V IH V IL tOE
tOD tOE
tOD tOEH
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL
tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCLZ tCP tCPA tCRP tCSH tCWD tCWL tDH tDS
-6 MAX 25 MIN 45 0 0 49 13 15 10 10 0 10 28 35 5 45 35 10 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tOD tOE tOEH tPC tPRWC tRAC tRAD tRAH tRASP tRCD tRCS tRP tRSH tRWD tRWL tWP
-5 MIN 0 8 20 47 50 9 9 50 11 0 30 13 67 13 5 12 10 60 14 0 40 15 79 15 5 MAX 12 12 MIN 0 10 25 56
-6 MAX 15 15 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 42 8 8 0 8 5 38 28 8 8 0
60
10,000
125,000
125,000
NOTE: 1. tPC is for LATE WRITE only.
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
14
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
FAST-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE)
t RASP V IH V IL t RSH t CSH t CRP CAS# V IH V IL t AR t RAD t ASR ADDR V IH V IL t RAH t ASC t CAH t ASC t CAH t RCD t CAS t CP t PC t CAS t CP t RP
RAS#
ROW
COLUMN
COLUMN t CWL
ROW
t RCS t WCS WE# V IH V IL t CAC t CLZ V OH V OL NOTE 1 t OFF t DS VALID DATA t AA t RAC
t RWL t WP t WCH
t DH
DQ
OPEN
VALID DATA
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA
tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCRP tCSH tCWL tDH tDS
-6 MAX 25 MIN 45 0 0 13 15 10 10,000 10 0 10 5 45 10 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOFF
tPC tRAC tRAD tRAH tRASP tRCD tRCS tRP tRSH tRWL tWCH tWCS tWP
-5 MIN 0 20 50 9 9 50 11 0 30 13 13 8 0 5 125,000 12 10 60 14 0 40 15 15 10 0 5 MAX 12 MIN 0 25
-6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 8 8 0 8 5 38 8 8 0
125,000
NOTE: 1. Do not drive data prior to tristate.
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
15
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON'T CARE)
tRC tRAS V IH V IL tCRP V IH V IL tASR ADDR V IH V IL tRAH tRPC tRP
RAS#
CAS#
ROW
ROW
V DQ V OH OL
OPEN
CBR REFRESH CYCLE (Addresses and OE# = DON'T CARE)
tRP RAS# V IH V IL tRPC tCP CAS# V IH V IL V OH V OL tWRP WE# V IH V IL tWRH OPEN tWRP tWRH tCSR tCHR tRPC tCSR tCHR tRAS NOTE 1 tRP tRAS
DQ
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tASR
tCHR tCP tCRP tCSR tRAH
-6 MAX MIN 0 10 10 5 5 10 MAX UNITS ns ns ns ns ns ns SYMBOL tRAS
tRC tRP tRPC tWRH tWRP
-5 MIN 50 84 30 5 8 8 MAX 10,000 MIN 60 104 40 5 10 10
-6 MAX 10,000 UNITS ns ns ns ns ns ns
MIN 0 8 8 5 5 9
NOTE: 1. End of CBR REFRESH cycle.
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
16
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
HIDDEN REFRESH CYCLE 1 (WE# = HIGH; OE# = LOW)
tRAS RAS# V IH V IL tCRP V IH V IL tAR tRAD tASR V IH V IL tRAH tASC tCAH tRCD tRSH tCHR tRP tRAS
CASL#/CASH#
ADDR
ROW
COLUMN tAA tRAC tCAC tCLZ tOFF
V DQx V IOH IOL
OPEN t OE t ORD
VALID DATA tOD
OPEN
OE#
V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL
tAA tAR tASC tASR tCAC tCAH tCHR tCLZ tCRP tOD
-6 MAX 25 MIN 45 0 0 13 15 10 10 0 5 12 0 15 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL tOE tOFF tORD tRAC
tRAD tRAH tRAS tRCD tRP tRSH
-5 MIN 0 0 9 9 50 11 30 13 10,000 MAX 12 12 50 12 10 60 14 40 15 MIN 0 0
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns 10,000 ns ns ns ns
MIN 38 0 0 8 8 0 5 0
NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
17
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
SELF REFRESH CYCLE (Addresses and OE# = DON'T CARE)
tRP RAS# V IH V IL tRPC tCP CAS# V IH V IL OPEN tWRP WE# V IH V IL tWRH tWRP tWRH tCSR tCHR tRPC tCSR tCHR tRAS tRP tRAS
Q
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tCHD tCP tCSR tRASS tRP MIN 15 8 5 100 30 MAX MIN 15 10 5 100 40 -6 MAX UNITS ns ns ns s ns SYMBOL tRPC tRPS tWRH tWRP MIN 5 90 8 8 -5 MAX MIN 5 105 10 10 -6 MAX UNITS ns ns ns ns
NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode. 2. Once tRPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh is used.
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
18
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
24/26-PIN PLASTIC SOJ (300 mil)
.679 (17.25) .673 (17.09)
.305 (7.75) .299 (7.59) .340 (8.64) .330 (8.38)
PIN #1 INDEX
.050 (1.27) TYP .600 (15.24) TYP
.037 (0.94) MAX DAMBAR PROTRUSION
.032 (0.81) .026 (0.66)
.105 (2.67) .090 (2.29)
.112 (2.84) .102 (2.59)
.142 (3.61) .132 (3.35) SEATING PLANE .020 (0.51) .015 (0.38) .040 (1.02) R .030 (0.76) .275 (6.99) .260 (6.61)
NOTE:
MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 1. All dimensions in inches (millimeters)
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
19
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 4 FPM DRAM
24/26-PIN PLASTIC TSOP (300 mil)
.678 (17.23) .672 (17.07) 26
SEE DETAIL A
.367 (9.32) .359 (9.12) .302 (7.67) .298 (7.57)
1 PIN #1 INDEX .050 (1.27) TYP .020 (0.50) .012 (0.30)
13
.007 (0.18) .005 (0.13)
.004 (0.10) .047 (1.20) MAX .008 (0.20) .002 (0.05) DETAIL A
.010 (0.25)
GAGE PLANE
SEATING PLANE .024 (0.60) .016 (0.40) .0315 (0.80) TYP
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc.
4 Meg x 4 FPM DRAM D49_5V.p65 - Rev. 5/00
20
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.

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